Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors

The authors present a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantisation in a cascade architecture to obtain high resolution with a low oversampling ratio. It is less sensitive to the nonlinearity of the digital-to-analogue (DAC) than those previously reported, thus enabling the use of very simple analogue circuitry with neither calibration nor trimming required