DocumentCode :
1373703
Title :
FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range
Author :
Chen, Poki ; Chen, Po-Yu ; Lai, Juan-Shan ; Chen, Yi-Jin
Author_Institution :
Dept. of Electron. Eng. & Grad. Inst. of Electro-Opt. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
Volume :
57
Issue :
6
fYear :
2010
fDate :
6/1/2010 12:00:00 AM
Firstpage :
1134
Lastpage :
1142
Abstract :
The first FPGA multiple channel digital-to-time converter, or digital pulse generator, is proposed to further extend FPGA applications into analog domain. Based on vernier principle, the effective resolution is made equivalent to the period difference of two phase-locked loop (PLL) outputs. The finer than ever DTC resolution of 1.58 ps is achieved with an Altera Stratix III FPGA chip. The DNL and INL are verified to be -0.086 ~ +0.12 LSB and -0.93 ~ +0.75 LSB respectively for input value varied from 1 to 1026. The widest operation range of 59.3 minutes is accomplished with 51 functioning input bits. Except for 2 shared PLLs, there are only 422 combinational ALUTs and 84 dedicated logic registers utilized per channel for 224-channel circuit implementation. The power consumption per channel is simulated to be 3.04 mW only. With a simple but powerful structure, the design cost is substantially reduced from those of its predecessors.
Keywords :
convertors; field programmable gate arrays; phase locked loops; pulse generators; FPGA Vernier digital-to-time converter; FPGA multiple channel digital-to-time converter; digital pulse generator; logic registers; phase-locked loop; time 59.3 min; ATE; BIST; FPGA and vernier principle; digital pulse generator; digital-to-time converter;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2009.2028748
Filename :
5371812
Link To Document :
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