Title :
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line
Author :
Woorham Bae ; Gyu-Seob Jeong ; Kwanseo Park ; Sung-Yong Cho ; Yoonsoo Kim ; Deog-Kyoon Jeong
Author_Institution :
Dept. of Electr. & Comput. Eng., Seoul Nat. Univ., Seoul, South Korea
Abstract :
A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm2. Due to the wide jitter tracking bandwidth of DLL and the inherent jitter correlation between data and forwarded clock, the proposed receiver exhibits outstanding jitter tolerance whose corner frequency is higher than 300 MHz.
Keywords :
clocks; delay lines; delay lock loops; receivers; DLL; VCDL; bang-bang PD; bit rate 12.5 Gbit/s; data samples; forwarded-clock receiver; half-bit delay line; jitter correlation; sample swapping scheme; stuck locking; swapping edge; wide jitter tracking bandwidth; Bandwidth; CMOS integrated circuits; CMOS technology; Clocks; Delays; Jitter; Receivers; delay-locked loop; forwarded clock receiver; jitter tolerance; sample swapping; stuck locking;
Conference_Titel :
European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th
Conference_Location :
Venice Lido
Print_ISBN :
978-1-4799-5694-4
DOI :
10.1109/ESSCIRC.2014.6942118
