A low band cellular terminal antenna impedance tuner in 130nm CMOS-SOI technology

This paper presents a low band antenna impedance tuner in 130nm CMOS-SOI technology. It consists of three digitally controlled switched capacitor banks and two off-chip inductors and is intended for use in terminals supporting modern cellular standards like WCDMA and LTE. By using a negative gate bias in the off state, linearity can be improved and maintained. Measurements show an OIP3 exceeding +55dBm for all measured impedance states, which cover a VSWR of up to 5.4. The measured minimum loss is 1dB or lower in the frequency range from 700-900MHz with spurious emissions below -30dBm at +33dBm input power. The switched capacitors are implemented with eight stacked transistors to yield a voltage handling of at least 20V, and in order to handle the large voltages custom designed capacitors are used.