DocumentCode
1374133
Title
PROTEUS-Lite project: dedicated to developing a telecommunication-oriented FPGA and its applications
Author
Miyazaki, Toshiaki ; Takahara, Atsushi ; Murooka, Takahiro ; Katayama, Masaru ; Ichimori, Takaki ; Shirakawa, Kazuhiro ; Tsutsui, Akihiro ; Fukami, Kennosuke
Author_Institution
NTT Network Innovation Center, Yokosuka, Japan
Volume
8
Issue
4
fYear
2000
Firstpage
401
Lastpage
414
Abstract
This paper describes a project dedicated to developing an improved (in terms of usability) version of our previous telecommunication-oriented field programmable gate array (FPGA), and its applications. To achieve this goal, we adopt several challenging design strategies. First, we determine the new FPGA architecture based on a quantitative evaluation carried out to optimize the interaction between the FPGA and CAD algorithms. In addition, we create a new chip design environment that allows semi-automatic test pattern generation and cross-checking between logic and layout design. Furthermore, a dedicated CAD system is developed based on a consideration of the evaluation results and the characteristics of the FPGA. As a result of these design strategies, the FPGA and CAD system are well-balanced, and even though the FPGA has very rich routing resources, the routing process can be finished quickly without sacrificing application-circuit performance. The FPGA is applied to several reconfigurable systems for telecommunications, and is found to offer the required functions and good performance.
Keywords
circuit layout CAD; field programmable gate arrays; hardware-software codesign; integrated circuit layout; logic CAD; network routing; reconfigurable architectures; FPGA; PROTEUS-Lite project; application-circuit performance; chip design environment; dedicated CAD system; design strategies; quantitative evaluation; reconfigurable systems; routing resources; semi-automatic test pattern generation; telecommunication-oriented FPGA; Circuits; Design automation; Field programmable gate arrays; Hardware; Laboratories; Logic design; Pipelines; Routing; Test pattern generators; Usability;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.863619
Filename
863619
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