A computer simulation model for simulating distortion in FET resistors

The power law that governs harmonic distortion states that the second harmonic, when plotted as a function of input power, will have a slope of two on a log scale, and the third harmonic will have a slope of three. This power law is fundamental to the use of intercept points by radio-frequency circuit designers to predict distortion levels from a knowledge of the input signal level. It is shown in this paper that the standard formulation of field effect transistor (FET) models violates this power law for FETs biased at V_ds=0. The problem is shown to arise from discontinuities in the high order derivatives which occur because V_gsand V_gd are interchanged in the computer models when V_ds switches sign. A model is presented which does not switch these variables and the new model is shown to follow the correct power law