DocumentCode
1374361
Title
Positive Gate-Bias Temperature Stability of RF-Sputtered
Active-Layer Thin-Film Transistors
Author
Tsai, Yi-Shiuan ; Chen, Jian-Zhang
Author_Institution
Inst. of Appl. Mech., Nat. Taiwan Univ., Taipei, Taiwan
Volume
59
Issue
1
fYear
2012
Firstpage
151
Lastpage
158
Abstract
This paper investigates the positive gate-bias temperature stability of RF-sputtered bottom-gate Mg0.05Zn0.95O active-layer thin-film transistors (TFTs) annealed at 200 °C for 5 h and 350 °C for 30 min. Although the TFT devices initially exhibited similar electrical characteristics, the TFTs annealed at 350 °C demonstrated stability characteristics superior to those annealed at 200 °C. This result is due to the improved crystallinity and more stable phase with greater proportion of Zn replaced by Mg in the ZnO crystals. The results also reveal a hump shape in the subthreshold region of the transfer characteristics, which is induced by the positive gate-bias stress at elevated temperatures. The hump phenomenon was suppressed in the TFT annealed at 350 °C. The hump disappeared shortly after removing the positive gate bias, suggesting that this phenomenon was meta-stable and resulted from gate-bias-induced electric field. One possible mechanism responsible for the hump formation in the transfer curve is the gate-field-induced back-channel parasitic transistor. Alternatively, this hump phenomenon might have been due to the creation of meta-stable vacancies in which the neutral defects were thermally excited and released electrons into the active layer to form a leakage path when the TFTs were subjected to gate-bias stress at elevated temperatures.
Keywords
annealing; magnesium compounds; sputtered coatings; thermal stability; thin film transistors; zinc compounds; MgZnO; RF-sputtered active-layer thin-film transistors; annealing; gate-bias-induced electric field; gate-field-induced back-channel parasitic transistor; hump formation; leakage path; meta-stable vacancies; neutral defects; positive gate-bias temperature stability; subthreshold region; temperature 200 degC; temperature 350 degC; time 30 min; time 5 h; transfer curve; Annealing; Logic gates; Stress; Temperature; Thermal stability; Thin film transistors; Zinc oxide; Gate-bias stability; MgO; MgZnO; oxide thin-film transistors (TFTs); thermal stability;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2011.2172212
Filename
6078412
Link To Document