Title :
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications
Author :
Poulton, J.W. ; Dally, William J. ; Chen, Xia ; Eyles, J.G. ; Greer, T.H. ; Tell, S.G. ; Wilson, J.M. ; Gray, C.T.
Author_Institution :
Nvidia Corp., Durham, NC, USA
Abstract :
High-speed signaling over high density interconnect on organic package substrates or silicon interposers offers an attractive solution to the off-chip bandwidth limitation problem faced in modern digital systems. In this paper, we describe a signaling system co-designed with the interconnect to take advantage of the characteristics of this environment to enable a high-speed, low area, and low-power die to die link. Ground-Referenced Signaling (GRS) is a single-ended signaling system that eliminates the major problems traditionally associated with single-ended design by using the ground plane as the reference and signaling above and below ground. This design employs a novel charge pump driver that additionally eliminates the issue of simultaneous switching noise with data independent current consumption. Silicon measurements from a test chip implementing two 16-lane links, with forwarded clocks, in a standard 28 nm process demonstrate 20 Gb/s operation at 0.54 pJ/bit over 4.5 mm organic substrate channels at a nominal 0.9 V power supply voltage. Timing margins at the receiver are >0.3 UI at a BER of 10-12. We estimate BER 10-25 at the eye center.
Keywords :
CMOS integrated circuits; charge pump circuits; clocks; driver circuits; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; integrated circuit testing; low-power electronics; BER; CMOS technology; GRS; advanced packaging application; bit rate 20 Gbit/s; charge pump driver; clock; data independent current consumption; ground plane; ground-referenced signaling; ground-referenced single-ended short-reach serial link; high density interconnection; high-speed signaling system; low-power die to die link; modern digital system; off-chip bandwidth limitation problem; organic package substrate; organic substrate channel; power supply voltage; silicon interposer; single-ended signaling system; size 28 nm; switching noise elimination; timing margin; voltage 0.9 V; Charge pumps; Clocks; Communication system signaling; Noise; Receivers; Switches; Transmitters; Ground-referenced signaling; high-speed I/O; low-power I/O; serial link; transceiver;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2013.2279053