Interpolating time counter with 100 ps resolution on a single FPGA device

Author

Szplet, Ryszard ; Kalisz, Jozef ; Szymanowski, Rafal

Author_Institution

Mil. Univ. of Technol., Warsaw, Poland

Volume

49

Issue

4

fYear

2000

fDate

8/1/2000 12:00:00 AM

Firstpage

879

Lastpage

883

Abstract

This paper describes the logic and performance of an interpolating time counter integrated on a single FPGA device. The resolution of 100 ps (LSB) was obtained because of the new design of the FPGA delay lines used for precise time-to-digital conversion, and the use of enhanced CMOS FPGA technology. The worst-case random error of 170 ps has been lowered to 70 ps by software correction of the nonlinearity of the delay lines. The counter can measure time intervals from 0-43 s and frequency up to 200 MHz. The maximum power consumption of the counter chip is 260 mW

Keywords

CMOS logic circuits; analogue-digital conversion; delay lines; field programmable gate arrays; interpolation; 0 to 43 s; 200 MHz; 260 mW; FPGA delay lines; delay line nonlinearity; enhanced CMOS FPGA technology; interpolating time counter; picosecond resolution; precise time-to-digital conversion; single FPGA device; software correction; time interval measurement; worst-case random error; CMOS logic circuits; CMOS technology; Counting circuits; Delay lines; Error correction; Field programmable gate arrays; Frequency measurement; Logic devices; Semiconductor device measurement; Time measurement;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/19.863942

Filename

863942