Title :
Architecture Design of Versatile Recognition Processor for Sensornet Applications
Author :
Hori, Yuichi ; Hanai, Yuya ; Nishimura, Jun ; Kuroda, Tadahiro
Author_Institution :
Keio Univ., Yokohama, Japan
Abstract :
This article presents the multiobject parallel recognition architecture of a versatile recognition processor (VRP) that detects and recognizes objects from images, videos, sounds, and acceleration signals. It offers eight times better power efficiency than conventional object recognition processors, making it ideal for mobile application platforms and wireless sensor network systems.
Keywords :
logic design; microprocessor chips; object recognition; parallel architectures; wireless sensor networks; architecture design; better power efficiency; conventional object recognition; mobile application platforms; multiobject parallel recognition; sensornet applications; versatile recognition processor; wireless sensor network systems; Acceleration; Energy consumption; Face detection; Face recognition; Humans; Image recognition; Object recognition; Signal processing; Videos; Wireless sensor networks; AdaBoost; Haar-like feature; low power; real time; recognition; wireless sensor network;
Journal_Title :
Micro, IEEE
