Superscalar instruction issue in an asynchronous microprocessor

The implementation of the instruction issuer for a superscalar asynchronous microprocessor (SCALP) is described as a case study in asynchronous design. The issuer accepts five instructions at a time from the memory interface and issues them out of order to five parallel functional units. SCALP´s architecture is designed to reduce the complexity of the instruction issuer by removing the need to detect dependencies between instructions as they are issued. The design has a regular cellular structure suitable for VLSI implementation. The issue´s performance is sufficient that no bottleneck forms in the SCALP pipeline