Asynchronous FPGA architectures

Field programmable gate arrays (FPGAs) are of increasing importance as processor support devices, and as computational devices in their only right. Current synchronous FPGA architectures create problems for the implementation of asynchronous circuits, due to their creation of hazards, reordering of signals and lack of arbitration. The paper examines how the first generation of asynchronous FPGA architectures (MONTAGE, PGA-STC and STACC) tackle these problems