DocumentCode :
1375607
Title :
Estimating power consumption of CMOS circuits modelled as symbolic neural networks
Author :
Macii, E. ; Poncino, M.
Author_Institution :
Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
Volume :
143
Issue :
5
fYear :
1996
fDate :
9/1/1996 12:00:00 AM
Firstpage :
331
Lastpage :
336
Abstract :
The authors propose a new approach to the problem of estimating the average power consumption of a CMOS combinational circuit which is based on neural models. Given the gate level description of a circuit, they build the corresponding Hopfield neural network, store it, calculate the energy dissipated by the network and, finally, derive the power dissipated by the original circuit. All the operations above are executed in the symbolic domain, that is algebraic decision diagrams are used to represent and manipulate the graph specification of the neural network modelling the circuit. The approach is viable and computationally efficient. In addition, it produces power estimates which are, on average, as accurate as the ones computed by state-of-the-art power analysis tools
Keywords :
CMOS logic circuits; Hopfield neural nets; combinational circuits; power consumption; CMOS circuits; Hopfield neural network; algebraic decision diagrams; combinational circuit; gate level description; graph specification; power analysis tools; power consumption estimation; power estimates; symbolic domain; symbolic neural networks;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2387
Type :
jour
DOI :
10.1049/ip-cdt:19960633
Filename :
537226
Link To Document :
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