Testable on-the-fly carry-save multiplier by alternating input data

Montuschi and Ciminiera (1993) presented a carry-save multiplier without final addition. By utilising the don´t-care minterms in the original on-the-fly conversion logic and by modifying the summand circuits, the proposed carry-save multiplier can become a concurrent error detection (CED) scheme using a time redundancy technique, called the `alternating logic´ (AL) approach, under the cell fault model. The AL approach applies normal input data and alternated input data to the circuit under test (CUT) in two consecutive time steps, and both results should be bit-by-bit complemented to each other in the fault-free case; otherwise, the CUT is faulty. With a 1/(8n+14) delay in the normal computation [2/(8n+14) delay for the CED mode], where n is the operand length, the proposed scheme requires about an 18% area overhead and one extra pin