DocumentCode :
1376468
Title :
Structure Design Optimization and Reliability Analysis on a Pyramidal-Shape Three-Die-Stacked Package With Through-Silicon Via
Author :
Che, F.X. ; Lim, Sharon P S ; Chai, T.C. ; Zhang, Xiaowu
Author_Institution :
Inst. of Microelectron., Agency for Sci., Technol. & Res., Singapore, Singapore
Volume :
12
Issue :
2
fYear :
2012
fDate :
6/1/2012 12:00:00 AM
Firstpage :
201
Lastpage :
208
Abstract :
In this paper, the reliability of a pyramidal-shape three-die-stacked package with through-silicon via (TSV) is studied experimentally and numerically. The initially designed microbumps are located peripherally along the edge of the TSV die, which induces a concentrated bending force on the lower die when the upper die is stacked. Finite-element (FE) simulation results show that such bump layout induces large stress and deflection in the lower die under the die-stacking process. Three-point bend tests were conducted to determine the die strength. Die-stacking experiments were also carried out. The experimental results show that the bottom die cracks when the middle die is stacked and the middle die cracks when the top die is stacked even with a small stacking force. Consistent results have been obtained among FE simulation, die strength bend test, and die-stacking experiments. An optimal bump layout design is proposed, which adds some dummy bumps on the central area of the die to support the bending force induced by the die-stacking process. The optimal design significantly reduces the die stress level and deflection. Finally, a successful die-stacking process is achieved even using a larger stacking force.
Keywords :
finite element analysis; integrated circuit design; integrated circuit packaging; integrated circuit reliability; optimisation; three-dimensional integrated circuits; FE simulation; TSV; TSV die; bending force; bottom die; bump layout; die-stacking process; finite-element simulation; middle die; optimal bump layout design; pyramidal-shape three-die-stacked package; reliability analysis; structure design optimization; three-point bend tests; through-silicon via; upper die; Force; Layout; Numerical models; Reliability; Stacking; Stress; Through-silicon vias; Die-stack package; finite-element (FE) modeling; reliability; through-silicon via (TSV) die strength;
fLanguage :
English
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
Publisher :
ieee
ISSN :
1530-4388
Type :
jour
DOI :
10.1109/TDMR.2011.2176126
Filename :
6081917
Link To Document :
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