DocumentCode :
1376793
Title :
Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET´s
Author :
Yu, Bin ; Wann, Clement H J ; Nowak, Edward D. ; Noda, Kenji ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Volume :
44
Issue :
4
fYear :
1997
fDate :
4/1/1997 12:00:00 AM
Firstpage :
627
Lastpage :
634
Abstract :
The normal and reverse short-channel effect of LDD MOSFET´s with lateral channel-engineering (pocket or halo implant) has been investigated. An analytical model is developed which can predict Vth as a function of Leff, VDS, VBS, and pocket parameters down to 0.1-μm channel length. The new model shows that the Vth roll-up component due to pocket implant has an exponential dependence on channel length and is determined roughly by (Np)¼Lp. The validity of the model is verified by both experimental data and two-dimensional (2-D) numerical simulation. On the basis of the model, a methodology to optimize the minimum channel length Lmin is presented. The theoretical optimal pocket implant performance is to achieve an Lmin approximately 55~60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement. The process design window of pocket implant is analyzed. The design tradeoff between the improvement of short-channel immunity and the other device electrical performance is also discussed
Keywords :
MOSFET; ion implantation; semiconductor device models; 0.1 mum; LDD MOSFET; analytical model; channel length; deep-submicron MOSFET; design tradeoff; dual-gate CMOS process; electrical performance; halo implant; lateral channel-engineering; minimum channel length optimization; n-MOSFET; pocket implant; pocket parameters; process design window; quasi-two-dimensional Poisson equation; reverse short-channel effect; short-channel effect; short-channel immunity; threshold voltage; two-dimensional numerical simulation; Analytical models; CMOS technology; Doping; Implants; MOSFET circuits; Numerical simulation; Optimization methods; Predictive models; Threshold voltage; Two dimensional displays;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.563368
Filename :
563368
Link To Document :
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