Area-efficient layout design for CMOS output transistors

Author

Ker, Ming-Dou ; Wu, Chung-Yu ; Wu, Tain-Shun

Author_Institution

VLSI Design Dept., Ind. Technol. Res. Inst., Hsinchu, Taiwan

Volume

44

Issue

4

fYear

1997

fDate

4/1/1997 12:00:00 AM

Firstpage

635

Lastpage

645

Abstract

A novel layout design to effectively reduce the layout area of the thin-oxide NMOS and PMOS devices in CMOS output buffers with ESD consideration is proposed. With respect to the traditional finger-type layout, the large-dimension output NMOS and PMOS devices are realized by multiple octagonal cells. Without using extra ESD-optimization process, the output NMOS and PMOS devices in this octagon-type layout can provide higher driving/sinking current and better ESD robustness within a smaller layout area. The drain-to-bulk parasitic capacitance at the output node is also reduced by this octagon-type layout. Experimental results in a 0.6-μm CMOS process have shown that the output driving (sinking) current of CMOS output buffers in per unit layout area is increased 47.7% (34.3%) by this octagon-type layout. The HBM (MM) ESD robustness of this octagon-type output buffer in per unit layout area is also increased 41.5% (84.6%), as comparing to the traditional finger-type output buffer. This octagon-type layout design makes a substantial contribution to the submicron or deep-submicron CMOS IC´s in high-density and high-speed applications

Keywords

CMOS integrated circuits; MOSFET; electrostatic discharge; integrated circuit layout; integrated circuit measurement; integrated circuit reliability; 0.6 mum; CMOS output buffers; CMOS output transistors; ESD robustness; HBM robustness; area-efficient layout design; deep-submicron CMOS IC; drain-to-bulk parasitic capacitance; driving current; high-density high-speed applications; layout area reduction; multiple octagonal cells; sinking current; submicron CMOS IC; thin-oxide NMOS devices; thin-oxide PMOS devices; CMOS process; CMOS technology; Circuits; Degradation; Electrostatic discharge; Inverters; MOS devices; Parasitic capacitance; Protection; Robustness;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.563369

Filename

563369