An ultra low power CMOS motion detector

This paper proposes a CMOS motion detector which consumes extremely low power. CMOS image sensor pixels in this motion detector senses image and image data are converted into just one-bit by using clocked comparators. Because using one-bit data makes additional processing units simple, total power consumption of this CMOS motion detector can be reduced. That is, internal memory which is composed of the clocked gating schemes based on the flip-flop and XOR function which compares a current image with a previous one in order to detect a difference are main features for the simple structure. However one-bit data process has a critical problem that it is hard to detect a motion when image inclines to white or block. For solving this problem, reference voltage controller which makes about the same proportion of white and block is implemented. We have made a test module of the proposed CMOS motion detector and tested it by using FPGA. According to the measurement result, total power consumption is about 32 ¿W at 3.3 V. Therefore, this motion detector can be useful for portable battery-operated devices.