Title :
Germanium Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated by Complementary-Metal–Oxide–Semiconductor-Compatible Process
Author :
Peng, J.W. ; Singh, N. ; Lo, G.Q. ; Bosman, M. ; Ng, C.M. ; Lee, S.J.
Author_Institution :
Silicon Nano Device Lab., Nat. Univ. of Singapore, Singapore, Singapore
Abstract :
This work presents a complementary metal-oxide-semiconductor-compatible top-down fabrication of Ge nanowires along with their integration into pMOSFETs with "HfO2/TaN" high-k/metal gate stacks. Lateral Ge wires down to 14 nm in diameter are achieved using a two-step dry etch process on a high-quality epitaxial Ge layer. To improve the interface quality between the Ge nanowire and the HfO2, thermally grown GeO2 and epitaxial-Si shells are used as interlayers. Devices with a GeO2 shell demonstrated excellent ION/IOFF ratios (>; 106), whereas the epitaxial-Si shell was found to improve the field-effect mobility of the holes in Ge nanowires to 254 cm2V-1 · s-1.
Keywords :
CMOS integrated circuits; MOSFET; elemental semiconductors; etching; germanium; germanium compounds; hafnium compounds; high-k dielectric thin films; nanowires; semiconductor epitaxial layers; semiconductor growth; silicon; Ge; GeO2; HfO2-TaN; Si; complementary-metal-oxide-semiconductor-compatible process; epitaxial-Si shells; field-effect mobility; germanium nanowire metal-oxide-semiconductor field-effect transistor; high-k-metal gate stacks; high-quality epitaxial layer; interface quality; pMOSFET; size 14 nm; two-step dry etch process; Epitaxial growth; Etching; Logic gates; MOSFET circuits; MOSFETs; Silicon; Core/shell (C/S); germanium (Ge); metal–oxide–semiconductor field-effect transistor (MOSFET); nanowire (NW); top–down;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2010.2088125