DocumentCode :
1377517
Title :
Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation
Author :
Toyota, Yoshiaki ; Matsumura, Mieko ; Hatano, Mutsuko ; Shiba, Takeo ; Ohkura, Makoto
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
Volume :
57
Issue :
2
fYear :
2010
Firstpage :
429
Lastpage :
436
Abstract :
The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.
Keywords :
CMOS integrated circuits; invertors; thin film transistors; CMOS inverter operation; DAHC stress; DAHC-stress-induced trapped electrons; LDD structure; NBT stress; SD structure; degradation characteristics; drain-avalanche hot-carrier stress; electron injections; gate voltage; high drain voltage; hole injections; lightly doped drain structure; n-channel polycrystalline-silicon TFT; negative-bias-temperature stress; p-channel polycrystalline-silicon TFT; single-drain structure; thin-film transistors; threshold voltage; Charge carrier processes; Circuit testing; Degradation; Drain avalanche hot carrier injection; Electron traps; Hot carriers; Inverters; Stress; Thin film transistors; Threshold voltage; complimentary metal–oxide–semiconductor (CMOS); drain-avalanche hot-carrier (DAHC) stress; electron injection; hole injection; inverter stress; negative-bias-temperature (NBT) stress; thin-film transistor (TFT) circuit; transient stress;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2009.2036808
Filename :
5373878
Link To Document :
بازگشت