Title :
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
Author :
Tu, Ming-Hsien ; Lin, Jihi-Yu ; Tsai, Ming-Chien ; Jou, Shyh-Jye ; Chuang, Ching-Te
Author_Institution :
Electron. Eng. Dept. & Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V VDD, an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.
Keywords :
CMOS memory circuits; SRAM chips; CMOS technology; asymmetrical write-assist cell virtual ground biasing scheme; bit rate 4 kbit/s; positive feedback sensing keeper scheme; power 10.4 muW; read static noise margin; single-ended subthreshold SRAM; size 90 nm; voltage 0.2 V; write margin; CMOS technology; Low power electronics; Low voltage; SRAM chips; Low power; low voltage; single-ended SRAM;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2010.2071690
