DocumentCode :
1377970
Title :
Novel Low- 
Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI
Author :
Luo, Xiaorong ; Wang, Yuangang ; Deng, Hao ; Fan, Jie ; Lei, Tianfei ; Liu, Yong
Author_Institution :
State key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Volume :
57
Issue :
2
fYear :
2010
Firstpage :
535
Lastpage :
538
Abstract :
A high-voltage lateral double diffused metal-oxide-semiconductor transistor on partial silicon on insulator (PSOI) with a buried low-k dielectric (LK PSOI) is proposed. The low-k value enhances the electric field strength in the dielectric (EI). The Si window not only makes the substrate share the breakdown voltage (BV) and modulates the field distribution in the SOI layer but also alleviates the self-heating effect. Compared with those of the conventional PSOI, the EI and BV of LK PSOI with kI = 2 are enhanced by 74% and 19%, respectively.
Keywords :
MOSFET; dielectric materials; silicon-on-insulator; breakdown voltage; buried low-k dielectric; electric field strength; high voltage LDMOS; high voltage lateral double diffused metal oxide semiconductor transistor; partial SOI; partial silicon on insulator; Dielectric breakdown; Dielectric devices; Dielectric substrates; Doping; Laboratories; Metal-insulator structures; Permittivity; Silicon on insulator technology; Thermal conductivity; Thin film circuits; Voltage; Breakdown voltage; electric fields; low- $k$
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2009.2037372
Filename :
5373943
Link To Document :
