Investigation of Sub-10-nm Diameter, Gate-All-Around Nanowire Field-Effect Transistors for Electrostatic Discharge Applications

Author

Liu, W. ; Liou, J.J. ; Jiang, Y. ; Singh, N. ; Lo, G.Q. ; Chung, J. ; Jeong, Y.H.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA

Volume

9

Issue

3

fYear

2010

fDate

5/1/2010 12:00:00 AM

Firstpage

352

Lastpage

354

Abstract

Electrostatic discharge (ESD) robustness of a promising nanoscaled device, the gate-all-around nanowire field-effect transistor (NW FET), was characterized for the first time using the transmission-line pulsing technique. The effects of gate length, nanowire dimension, and nanowire count on the failure current, leakage current, trigger voltage, and on-resistance were investigated. ESD performances of the gate-all-around NW FET and other nanostructure devices, such as the poly-Si nanowire thin-film transistor and FinFET were also compared and discussed.

Keywords

electrostatic discharge; field effect transistors; nanowires; transmission lines; FinFET; electrostatic discharge applications; failure current; gate-all-around nanowire field-effect transistors; leakage current; nanoscaled device; nanostructure devices; nanowire dimension; size 10 nm; thin-film transistor; transmission-line pulsing technique; Electrostatic discharge (ESD); failure current; leakage current ($I_{rm leakage}$); nanowire; on-resistance ($R_{rm on}$);

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2009.2038225

Filename

5373953