Title :
High performance VLSI architecture for division and square root
Author :
McCanny, J.V. ; Woods, R.F.
Abstract :
A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.
Keywords :
VLSI; digital arithmetic; digital signal processing chips; parallel architectures; VLSI architecture; VLSI design; array size independent; digital signal processing; division; high performance bit; parallel architecture; redundant arithmetic; semisystolic schedule; square root;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19910013
