• DocumentCode
    1378868
  • Title

    High performance VLSI architecture for division and square root

  • Author

    McCanny, J.V. ; Woods, R.F.

  • Volume
    27
  • Issue
    1
  • fYear
    1991
  • Firstpage
    19
  • Lastpage
    21
  • Abstract
    A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.
  • Keywords
    VLSI; digital arithmetic; digital signal processing chips; parallel architectures; VLSI architecture; VLSI design; array size independent; digital signal processing; division; high performance bit; parallel architecture; redundant arithmetic; semisystolic schedule; square root;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19910013
  • Filename
    60841
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1378868