DocumentCode
1378997
Title
Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement
Author
Zheng, Hao ; Yao, Haiqiong ; Yoneda, Tomohiro
Author_Institution
Dept. of Comput. Sci. & Eng. (CSE), Univ. of South Florida, Tampa, FL, USA
Volume
59
Issue
4
fYear
2010
fDate
4/1/2010 12:00:00 AM
Firstpage
561
Lastpage
573
Abstract
Divide-and-conquer is essential to address state explosion in model checking. Verifying each individual component in a system, in isolation, efficiently requires an appropriate context, which traditionally is obtained by hand. This paper presents an efficient modular model checking approach for asynchronous design verification. It is equipped with a novel abstraction refinement method that can refine a component abstraction to be accurate enough for successful verification. It is fully automated, and eliminates the need of finding an accurate context when verifying each individual component, although such a context is still highly desirable. This method is also enhanced with additional state space reduction techniques. The experiments on several nontrivial asynchronous designs show that this method efficiently removes impossible behaviors from each component including ones violating correctness requirements.
Keywords
formal verification; state-space methods; abstraction refinement; abstraction refinement method; large asynchronous designs; modular model checking; state explosion; state space reduction techniques; Engineering profession; Explosions; Informatics; Logic circuits; State-space methods; Formal methods; abstraction; circuit verification; logic verification; model checking; modular verification; refinement.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2009.187
Filename
5374376
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