DocumentCode :
1379034
Title :
To SAT or Not to SAT: Scalable Exploration of Functional Dependency
Author :
Jiang, Jie-Hong Roland ; Chih-Chun Lee ; Mishchenko, A. ; Chung-Yang Huang
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
59
Issue :
4
fYear :
2010
fDate :
4/1/2010 12:00:00 AM
Firstpage :
457
Lastpage :
467
Abstract :
Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1,??,gn}, i.e., f = h(g1,??,gn). It plays an important role in many aspects of electronic design automation (EDA). Prior approaches to the exploration of functional dependency are based on binary decision diagrams (BDDs), which may not be easily scalable to large designs. This paper formulates both single-output and multiple-output functional dependencies as satisfiability (SAT) solving and exploits extensively the capability of a modern SAT solver. Thereby, functional dependency can be detected effectively through incremental SAT solving, and the dependency function h, if it exists, is obtained through Craig interpolation. The proposed method enables (1) scalable detection of functional dependency, (2) fast enumeration of dependency function under a large set of candidate base functions, and (3) potential application to large-scale logic synthesis and formal verification. Experimental results show that the proposed method is far superior to prior work and scales well in dealing with the largest ISCAS and ITC benchmark circuits with up to 200 K gates.
Keywords :
Boolean functions; binary decision diagrams; computability; electronic design automation; logic design; SAT solver; base functions; binary decision diagrams; dependency function; electronic design automation; formal verification; functional dependency; large-scale logic synthesis; multiple-output functional dependencies; rewriting a Boolean function; satisfiability; single-output functional dependencies; Boolean functions; Cost accounting; Data mining; Data structures; Interpolation; Junctions; Probability density function; Automatic synthesis; design aids; logic design; optimization.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2010.12
Filename :
5374381
Link To Document :
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