Title :
A comparative performance study of LDPC and Turbo codes for realistic PLC channels
Author :
Prasad, Girijesh ; Latchman, H.A. ; Youngjoon Lee ; Finamore, W.A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
fDate :
March 30 2014-April 2 2014
Abstract :
Turbo codes are attractive compared with Low Density Parity Check (LDPC) codes for Forward Error Correction (FEC) applications mainly due to their superior performance, especially at low Signal-to-Noise Ratio (SNR) such as are common in Powerline channels. For example, IEEE 1901-FFT PHY used the Turbo coding scheme defined in the HomePlug AV standards. However, patent fees are usually required for each turbo-code enabled manufactured device. The objective of this paper is to examine whether unlicensed LDPC codes, with optimized choices of block lengths, could be a viable alternative for future Powerline Communications (PLC) applications. The paper shows that the performance of the LDPC codes can approximate that of the Turbo codes with higher block lengths, on channels with typical and realistic PLC characteristics. The paper also shows that the additional complexity associated with this increase in block length can be mitigated by the use of Quasi-Cyclic LDPC (QC-LDPC) codes.
Keywords :
carrier transmission on power lines; cyclic codes; forward error correction; parity check codes; turbo codes; FEC; HomePlug AV standards; IEEE 1901-FFT PHY; QC-LDPC codes; SNR; block lengths; forward error correction applications; low density parity check codes; low signal-to-noise ratio; patent fees; powerline channels; powerline communications; quasi-cyclic LDPC codes; realistic PLC channels; turbo coding scheme; unlicensed LDPC codes; Bit error rate; Iterative decoding; Noise; Turbo codes; HomePlug AV; QC-LDPC; Turbo codes; code rate;
Conference_Titel :
Power Line Communications and its Applications (ISPLC), 2014 18th IEEE International Symposium on
Conference_Location :
Glasgow
DOI :
10.1109/ISPLC.2014.6812365