DocumentCode :
1379122
Title :
A CMOS continuous-time Gm-C filter for PRML read channel applications at 150 Mb/s and beyond
Author :
Mehr, Iuri ; Welland, David R.
Author_Institution :
Analog Devices Inc., Wilmington, MA, USA
Volume :
32
Issue :
4
fYear :
1997
fDate :
4/1/1997 12:00:00 AM
Firstpage :
499
Lastpage :
513
Abstract :
Design techniques for equiripple phase CMOS continuous-time filters are presented, and their integration within a partial-response maximum likelihood (PRML) disk drive read channel is discussed. A programmable seven-pole two asymmetric zero filter implementation is described based on a new transconductance (Gm) cell. The impact of integrator finite output impedance, excess phase, and other implementation related nonidealities is discussed. A filter tuning circuit that requires an accurate time base but no external components is presented. The filter has a cutoff frequency (fc) range of 6-43 MHz, where fc is the -3 dB point of the magnitude transfer function with the two zeros set to infinity. Also, with finite zeros it is able to provide up to 12 dB of boost which is defined as the maximum value of the magnitude transfer function referred to dc. The group delay ripple stays within ±2% for frequencies below 1.75 f c. The cutoff frequency exhibits a 650 ppm/°C temperature dependency and a variation of ±1%/V with the power supply. Total harmonic distortion (THD) values are below -40 dB at twice the nominal operating input voltage (Vnominal=320 mV peak-to-peak differential), and the dynamic range exceeds 60 dB (for a maximum input signal of 640 mV peak-to-peak differential, maximum bandwidth setting, and no boost). Both the filter and a tuning circuit were implemented in a 0.6-μm single-poly triple-metal n-well CMOS process. They consume 90 mW from a single 5 V power supply and occupy an area of 0.8 mm2
Keywords :
CMOS integrated circuits; circuit tuning; continuous time filters; hard discs; harmonic distortion; integrating circuits; maximum likelihood detection; partial response channels; programmable filters; transfer functions; 150 Mbit/s; 5 V; 6 to 43 MHz; 90 mW; CMOS continuous-time Gm-C filter; PRML read channel applications; accurate time base; cutoff frequency; disk drive read channel; dynamic range; equiripple phase; excess phase; filter tuning circuit; group delay ripple; integrator finite output impedance; magnitude transfer function; partial-response maximum likelihood; programmable seven-pole two asymmetric zero filter; single-poly triple-metal n-well CMOS process; total harmonic distortion; tuning circuit; Circuit optimization; Cutoff frequency; Delay; Disk drives; Filters; H infinity control; Impedance; Power supplies; Transconductance; Transfer functions;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.563671
Filename :
563671
Link To Document :
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