An analog VLSI neural network with on-chip perturbation learning

Author

Montalvo, Antonio J. ; Gyurcsik, Ronald S. ; Paulos, John J.

Author_Institution

Ericsson Inc., Research Triangle Park, NC, USA

Volume

32

Issue

4

fYear

1997

fDate

4/1/1997 12:00:00 AM

Firstpage

535

Lastpage

543

Abstract

An analog very large scale integration (VLSI) neural network intended for cost-sensitive, battery-powered, high-volume applications is described. Weights are stored in the analog domain using a combination of dynamic and nonvolatile memory that allows both fast learning and reliable long-term storage. The synapse occupies 4.9 K μm² in a 2-μm technology. On-chip controlled perturbation-based gradient descent allows fast learning with very little external support. Other distinguishing features include a reconfigurable topology and a temperature-independent feedforward path. An eight-neuron, 64-synapse proof-of-concept chip reliably solves the exclusive-or problem in ten´s of milliseconds and 4-b parity in hundred´s of milliseconds

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; feedforward neural nets; learning (artificial intelligence); neural chips; 2 micron; 4 bit; analog VLSI neural network; dynamic memory; exclusive-or problem; long-term storage; nonvolatile memory; on-chip perturbation learning; perturbation-based gradient descent; reconfigurable topology; synapse; temperature-independent feedforward path; Backpropagation algorithms; CMOS technology; Circuits; Network topology; Network-on-a-chip; Neural networks; Neurons; Nonvolatile memory; Temperature; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.563675

Filename

563675