DocumentCode
1379167
Title
The delay vernier pattern generation technique
Author
Moyer, Gary C. ; Clements, Mark ; Lui, W. ; Schaffer, Toby ; Cavin, Ralph K., III
Author_Institution
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Volume
32
Issue
4
fYear
1997
fDate
4/1/1997 12:00:00 AM
Firstpage
551
Lastpage
562
Abstract
The authors describe a new technique for generating an arbitrary digital data stream with very fine timing resolution. Note that this timing resolution specifies the output edge placement precision, not the bit rate. The resolution is determined by the difference between two propagation delays rather than by an absolute delay. Because this difference can be made very small, the circuit, called the delay vernier generator, can achieve unprecedented timing resolution in a particular circuit technology. Also, this very precise timing is obtained without requiring an extremely high speed clock. The generator architecture includes delay-locked loop calibration mechanisms to compensate for process and temperature variations. A prototype chip was fabricated in a 1.2-μm CMOS technology, and measurements confirmed that resolutions as fine as 100 ps can be achieved reliably
Keywords
CMOS digital integrated circuits; calibration; delay circuits; signal generators; timing; 1.2 micron; CMOS technology; calibration mechanisms; delay vernier pattern generation technique; delay-locked loop; output edge placement precision; propagation delays; temperature variations; timing resolution; Bit rate; CMOS technology; Calibration; Circuits; Clocks; Propagation delay; Prototypes; Semiconductor device measurement; Temperature; Timing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.563677
Filename
563677
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