• DocumentCode
    1379393
  • Title

    Inserting scan at the behavioral level

  • Author

    Aktouf, Chouki ; Fleury, Hérvé ; Robach, Chantal

  • Author_Institution
    Nat. Polytech. Inst., Grenoble, France
  • Volume
    17
  • Issue
    3
  • fYear
    2000
  • Firstpage
    34
  • Lastpage
    42
  • Abstract
    This article presents a method for inserting test logic at the behavioral level of a VHDL design description. The method is easy to use, and in most cases it requires lower area overhead than classical scan insertion methods
  • Keywords
    hardware description languages; logic CAD; logic testing; VHDL design description; behavioral level; scan insertion; test logic; Benchmark testing; Circuit synthesis; Concurrent computing; Flip-flops; Hardware design languages; Libraries; Logic design; Logic testing; Process design; Registers;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.867892
  • Filename
    867892
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1379393