Title :
Inserting scan at the behavioral level
Author :
Aktouf, Chouki ; Fleury, Hérvé ; Robach, Chantal
Author_Institution :
Nat. Polytech. Inst., Grenoble, France
Abstract :
This article presents a method for inserting test logic at the behavioral level of a VHDL design description. The method is easy to use, and in most cases it requires lower area overhead than classical scan insertion methods
Keywords :
hardware description languages; logic CAD; logic testing; VHDL design description; behavioral level; scan insertion; test logic; Benchmark testing; Circuit synthesis; Concurrent computing; Flip-flops; Hardware design languages; Libraries; Logic design; Logic testing; Process design; Registers;
Journal_Title :
Design & Test of Computers, IEEE
