DocumentCode
1379465
Title
Architecture and reliability of fault tolerant bitonic sorter
Author
Tee-Hiang Cheng
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst.
Volume
34
Issue
4
fYear
1998
fDate
2/19/1998 12:00:00 AM
Firstpage
326
Lastpage
327
Abstract
Bitonic sorters are used in a number of telecommunication switching and digital signal processing systems, where any fault in the sorters may spell disaster. Unlike the conventional approach to enhance reliability using redundant sorters, the author presents a sorter with internal redundant sorting elements and evaluates its fault tolerance
Keywords
VLSI; failure analysis; integrated circuit reliability; redundancy; reliability theory; signal processing; sorting; telecommunication switching; DSP systems; digital signal processing systems; fault tolerance evaluation; fault tolerant bitonic sorter; internal redundant sorting elements; reliability; telecommunication switching;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19980253
Filename
675668
Link To Document