DocumentCode
1379551
Title
Four-phase improved adiabatic pseudo-domino logic
Author
Lau, K.T. ; Liu, F.
Author_Institution
Mircroelectron. Centre, Nanyang Technol. Inst., Singapore
Volume
34
Issue
4
fYear
1998
fDate
2/19/1998 12:00:00 AM
Firstpage
343
Lastpage
344
Abstract
A four-phase improved adiabatic pseudo-domino logic family is presented. The proposed logic family, IAPDL-4φ, is an extension of IAPDL (improved adiabatic pseudo-domino logic). It has the same circuit structure as IAPDL, but a different clocking system is applied. A four-phase clock-supply to facilitate pipelining of the design is used in addition to a reduced pulsewidth for the auxiliary clocks. As a result, the speed is improved by about a factor of two, and power dissipation is decreased by ~65% for various shift registers at 200 MHz, compared to IAPDL
Keywords
clocks; pipeline processing; sequential circuits; shift registers; 200 MHz; IAPDL-4φ; adiabatic pseudo-domino logic; clocking system; four-phase logic family; pipelining; power dissipation; pulsewidth; shift registers;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19980303
Filename
675682
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