Abstract :
A four-phase improved adiabatic pseudo-domino logic family is presented. The proposed logic family, IAPDL-4φ, is an extension of IAPDL (improved adiabatic pseudo-domino logic). It has the same circuit structure as IAPDL, but a different clocking system is applied. A four-phase clock-supply to facilitate pipelining of the design is used in addition to a reduced pulsewidth for the auxiliary clocks. As a result, the speed is improved by about a factor of two, and power dissipation is decreased by ~65% for various shift registers at 200 MHz, compared to IAPDL
