• DocumentCode
    1379787
  • Title

    Dynamic Task Mapping for MPSoCs

  • Author

    de Souza Carvalho, Ewerson Luiz ; Calazans, Ney Laert Vilar ; Moraes, Fernando Gehm

  • Author_Institution
    Pontificia Univ. Catolica do Rio Grande do Sul, Porto Alegre, Brazil
  • Volume
    27
  • Issue
    5
  • fYear
    2010
  • Firstpage
    26
  • Lastpage
    35
  • Abstract
    Multiprocessor-system-on-a-chip (MPSoC) applications can consist of a varying number of simultaneous tasks and can change even after system design, enforcing a scenario that requires the use of dynamic task mapping. This article investigates dynamic task-mapping heuristics targeting reduction of network congestion in network-on-chip (NoC)-based MPSoCs. The proposed heuristics achieve up to 31% smaller channel load and up to 22% smaller packet latency than other heuristics.
  • Keywords
    multiprocessing systems; network-on-chip; dynamic task-mapping heuristics; multiprocessor-system-on-a-chip; network congestion reduction; network-on-chip-based MPSoC; Algorithm design and analysis; Artificial neural networks; Hardware; Heuristic algorithms; IP networks; Load modeling; Software; MPSoC; NoC; SoC; design and test; dynamic task mapping;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2010.106
  • Filename
    5638173
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1379787