Title :
A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
This paper describes a single-chip implementation of a low-voltage image-reject downconverter for a 5.1-5.8-GHz radio receiver. It consists of a low-noise preamplifier (LNA) that is simultaneously noise and power matched to the RF source, and dual doubly balanced mixers coupled to the LNA by a monolithic trifilar transformer. The image-reject architecture eliminates an RF filter, thereby simplifying packaging requirements. The downconverter realizes over 36 dB of image rejection while dissipating 24 mW from a 0.9 V supply, or 18.5 mW at 1.8 V. Conversion gain is 14 dB, IIP3=-5.5 dBm, and noise figure is 6.8 dB (single sideband 50 /spl Omega/) when operating from a 0.9 V supply.
Keywords :
Ge-Si alloys; MMIC frequency converters; MMIC mixers; bipolar MMIC; integrated circuit design; low-power electronics; preamplifiers; radio receivers; semiconductor materials; 0.9 to 1.8 V; 14 dB; 18.5 to 24 mW; 5.1 to 5.8 GHz; 6.8 dB; LNA; LV downconverter RF IC; SHF; SiGe; dual doubly balanced mixers; image-reject architecture; image-reject downconverter RFIC; low-noise preamplifier; low-voltage RF IC; monolithic trifilar transformer; packaging; single-chip implementation; wireless receiver; Filters; Gain; Image converters; Integrated circuit noise; Noise figure; Packaging; Preamplifiers; Radio frequency; Radiofrequency integrated circuits; Receivers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
