DocumentCode :
138095
Title :
Thermo-mechanical Stress of underfilled 3D IC packaging
Author :
Ming-Han Wang ; Mei-Ling Wu
Author_Institution :
Dept. of Mech. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fYear :
2014
fDate :
7-9 April 2014
Firstpage :
1
Lastpage :
5
Abstract :
In recent years, there has been a dramatic proliferation of research concerned with electronic products because of more various functions are integrate into the device and product´s size has become smaller. As a result of these functional requirements, through silicon via (TSV) was investigated, this are getting considerable attentions not only from reducing the packaging size but also from shortening the interconnection´s distance that can achieve the effect of enhancing signal transmission. TSVs are the vertical hole through the stacked IC, and they are also responsible for transferring signals between the ICs. Thus, they can improve the time delay of the signal transduction and allow better electrical performance than stacked ICs with wire bonding technology. However, a review of the literature indicates that electronic components will be affected easily by environmental factors such as humidity, pressure, and temperature. In general, the stacked ICs with TSV structure is easily affected by temperature changes than others factors since each material have different thermal expansion. In very recently, the stacked IC packaging has been primarily concerned with thermo-mechanical loadings than traditional single IC packaging, which leads some problems such as via cracking, die cracking and interfacial delamination and so on. The above problems not only affect the performance of the device but also lead the device fail. Hence, most of the studies [1-9] are focus on discussing thermal mechanical loading with simulation method. Some of them discuss the relationship between the TSV shape and the stresses [4, 5]. In addition, most of people just build local TSV structure to do their research [4-9]. Although it can save more time but it also increase the error percentage with real situation. And this paper build the three dimensional four layers stacked IC packaging model from Hsieh [1]´s paper which can more close to real situation. And setting the structure to be sim- lated from the temperature 150°C to -50°C which is as retreat temperature. This paper use ANSYS software which is based on finite element theory in order to reduce time used and save cost, as finite element simulation can provide results more quickly and cheaply than experiments. Moreover, the research mainly analyzes the maximum von-Mises stress in TSVs and micro-bumps. Besides, this paper will sort out geometries and material properties of underfill which will serious affect von-Mises stress value by Design of Experiments (DoE) analysis. Through the DoE analysis, the critical factors are selected as main design factors to reduce the von-Mises stresses. This study can provide the significant information to effectively design the products and increase the reliability. This information can also eliminate the testing time.
Keywords :
design of experiments; finite element analysis; integrated circuit modelling; integrated circuit packaging; stress analysis; thermal expansion; three-dimensional integrated circuits; ANSYS software; DoE analysis; TSV structure; design of experiment analysis; die cracking; electronic components; electronic products; environmental factors; finite element theory; interconnection distance; interfacial delamination; maximum von-Mises stress; microbumps; product size; signal transduction; signal transmission; stacked IC; temperature 150 degC to -50 degC; thermal expansion; thermo-mechanical loadings; thermo-mechanical stress; three dimensional four layers stacked IC packaging model; through silicon via; time delay; underfilled 3D IC packaging; vertical hole; wire bonding technology; Abstracts; Packaging; Silicon; Stress; Substrates; Thermomechanical processes; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems (eurosime), 2014 15th international conference on
Conference_Location :
Ghent
Print_ISBN :
978-1-4799-4791-1
Type :
conf
DOI :
10.1109/EuroSimE.2014.6813801
Filename :
6813801
Link To Document :
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