Title :
Circuit improvements for high-speed domino logic: for the Manchester carry chain
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
fDate :
2/5/1998 12:00:00 AM
Abstract :
Circuit techniques are introduced to reduce the delay of pass-transistor chains within the domino-logic implementation of a Manchester carry chain: the quadratic dependency on the number of bits is made linear without increasing transistor sizes
Keywords :
CMOS logic circuits; adders; carry logic; delays; logic design; Manchester carry chain; delay reduction; high-speed domino logic; pass-transistor chains;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980236
