A morphological filter chip using a modified decoding function

This paper proposes a new very large scale integration architecture for cost-effective morphological filters and presents its design and chip implementation. The proposed architecture can reduce the hardware cost by using a feedback loop path and a decoder/encoder pair comparator. The feedback loop path can reuse partial results to reduce the number of add/subtract units. The decoder/encoder pair comparator using a modified decoding function can reduce the gate count and propagation delay especially when the size of morphological operations increases. We used the 0.8-μm SOG cell library (KG60 K) and the total number of gates is only 2667. The proposed morphological filter chip has actually been fabricated and is running at 30 MHz that meets the real-time image processing requirement of the ITU-R BT.601 standard