A transformational approach to synthesizing combinational circuits

Author

Tai, S.-C. ; Du, M.W. ; Lee, R.C.T.

Author_Institution

Inst. of Comput. Sci., Nat. Tsing-Hua Univ., Hsinchu, Taiwan

Volume

10

Issue

3

fYear

1991

fDate

3/1/1991 12:00:00 AM

Firstpage

286

Lastpage

295

Abstract

VAR, a transformational approach for obtaining multilevel logic synthesis results, is described. Suppressed variable permutation and complementation (SVPC) transformations which are powerful and can be economically realized are introduced. Each SVPC transformation can be viewed as an identity mapping on the n-cube, except on an (n-r)-subcube (defined by r fixed coordinates), where it behaves like a variable permutation and complementation (VPC) transformation on n-r variables (the free variables). VAR is based on transforming the input functions to predefined goal functions by SVPC transformations. A transformation tree is obtained, and the transformations on the tree are collapsed and further simplified to obtain an economical circuit. This approach is illustrated by considering the sum function of the full adder

Keywords

combinatorial circuits; logic design; trees (mathematics); (n-r)-subcube; SVPC transformation; VAR; combinational circuits; economical circuit; multilevel logic synthesis; n-cube; predefined goal functions; sum function; suppressed variable permutation and complementation; transformation tree; transformational approach; Automation; Circuit synthesis; Combinational circuits; Genetic mutations; Helium; Logic circuits; Logic gates; Power generation economics; Reactive power; Silicon compiler;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.67783

Filename

67783