A low thermal budget self-aligned Ti silicide technology using germanium implantation for thin-film SOI MOSFET´s

Author

Liu, Ping ; Hsiao, Tommy C. ; Woo, Jason C S

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

45

Issue

6

fYear

1998

fDate

6/1/1998 12:00:00 AM

Firstpage

1280

Lastpage

1286

Abstract

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET´s is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET´s such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-μm SOI MOSFET´s are fabricated with good device characteristics

Keywords

MOSFET; annealing; contact resistance; semiconductor device metallisation; silicon-on-insulator; titanium compounds; TiSi₂; annealing temperature; contact resistance; device characteristics; dopant segregation; lateral voids; narrow gate; pre-amorphized layer; self-aligned silicide technology; silicidation temperature; silicide depth; thermal agglomeration; thermal budget; thin-film SOI MOSFETs; Amorphous silicon; Annealing; Contact resistance; Germanium; Silicidation; Silicides; Temperature control; Thermal resistance; Titanium; Transistors;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.678547

Filename

678547