FLAG: a flexible layout generator for analog MOS transistors

Author

Mathias, Herve ; Berger-Toussan, Josette ; Jacquemod, Gilles ; Gaffiot, Frederic ; Helley, Michel Le

Author_Institution

Lab. d´´Electron., Ecole Centrale de Lyon, Ecully, France

Volume

33

Issue

6

fYear

1998

fDate

6/1/1998 12:00:00 AM

Firstpage

896

Lastpage

903

Abstract

This paper describes a flexible MOS transistor layout generator which draws optimal layouts whatever the W and L dimensions. The drawing methodology is based on the use of small elementary parts, called bricks, which are placed side by side inside a user-specified boundary. The generated transistors may allow diffusion merging along whichever sides the user wishes and may have a global rectilinear shape. The internal structure of these cells may also be chosen by the designer so that it is well suited to his application. Transistors developed using this generator have been tested, and have been used to build a simple operational amplifier.

Keywords

CMOS analogue integrated circuits; MOSFET; circuit layout CAD; integrated circuit layout; operational amplifiers; FLAG; analog MOS transistors; drawing methodology; flexible layout generator; op amp layout; operational amplifier; user-specified boundary; Analog circuits; CMOS analog integrated circuits; Circuit testing; Design automation; MOSFETs; Merging; Operational amplifiers; Process design; Routing; Shape;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.678653

Filename

678653