Title :
A new class of sequential circuits with combinational test generation complexity
Author_Institution :
Graduate Sch. of Inf. Sci, Nara Inst. of Sci. & Technol., Japan
fDate :
9/1/2000 12:00:00 AM
Abstract :
We introduce a new class of sequential circuits with combinational test generation complexity which we call internally balanced structures. It is shown that sequential circuits can be classified by their structure as follows: (sequential circuits of acyclic structure) ⊃ (sequential circuits of internally balanced structure) ⊃ (sequential circuits of balanced structure) and that internally balanced structures allow test generation with combinational test generation complexity. On the other hand, if finite state machines (FSMs) are classified by their realization possibility, it can be shown that (FSMs which can be realized as a sequential circuit of acyclic structure)=(FSMs which can be realized as a sequential circuit of internally balanced structure) ⊃ (FSMs which can be realized as a sequential circuit of balanced structure). Hence, any FSM realizable with acyclic structure can also be realized with internally balanced structure which allows test generation with combinational test generation complexity. In addition, we discuss the definition of test generation possibility with combinational test generation complexity and introduce a new definition which covers the previous narrow definition. Finally, we study applications to design for testability based on the partial scan and to test generation time reduction for sequential circuits in general, using characteristics of the internally balanced structures. The experimental results show the effectiveness of this approach
Keywords :
design for testability; finite state machines; logic design; sequential circuits; acyclic structure; combinational test generation complexity; design for testability; finite state machines; internally balanced structures; partial scan; sequential circuits; Automata; Character generation; Circuit testing; Combinational circuits; Design for testability; Design methodology; Flip-flops; Large-scale systems; Sequential analysis; Sequential circuits;
Journal_Title :
Computers, IEEE Transactions on