A study of hot-carrier-induced mismatch drift: a reliability issue for VLSI circuits

Author

Huh, Yoonjong ; Sung, Yungkwon ; Kang, S.M.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

Volume

33

Issue

6

fYear

1998

fDate

6/1/1998 12:00:00 AM

Firstpage

921

Lastpage

927

Abstract

The mismatch drift of dynamic circuits, which must be corrected by precharging before activation, is a fundamental process and device reliability issue for very large scale integration (VLSI) circuits. In this paper, we report the consequences of hot-carrier effects on gate capacitance variation and its impact on the mismatch drift of MOS dynamic circuits. It is shown here that the impact of hot-carrier-induced gate capacitance variation on VLSI circuits is more critical than DC parameter (saturation current, threshold voltage, etc.) degradation. An electron beam probing was performed on a 64 Mb DRAM chip to detect the influence of gate capacitance variation in dynamic circuit blocks before and after hot-carrier stress

Keywords

CMOS integrated circuits; DRAM chips; MOS integrated circuits; VLSI; capacitance; hot carriers; integrated circuit reliability; 64 Mbit; DRAM chip; MOS dynamic circuits; VLSI circuits; electron beam probing; gate capacitance variation; hot-carrier stress; hot-carrier-induced mismatch drift; reliability issue; Capacitance; Circuit simulation; Circuit testing; Degradation; Hot carriers; Integrated circuit reliability; MOSFET circuits; Stress; Threshold voltage; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.678661

Filename

678661