DocumentCode :
1383926
Title :
3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS
Author :
Batude, Perrine ; Ernst, Thomas ; Arcamone, Julien ; Arndt, Gregory ; Coudrain, Perceval ; Gaillardon, Pierre-Emmanuel
Author_Institution :
CEA-leti, Grenoble, France
Volume :
2
Issue :
4
fYear :
2012
Firstpage :
714
Lastpage :
722
Abstract :
3-D sequential integration stands out from other 3-D schemes as it enables the full use of the third dimension. Indeed, in this approach, 3-D contact density matches with the transistor scale. In this paper, we report on the main advances enabling the demonstration of functional and performant stacked CMOS-FETs; i.e., wafer bonding, low temperature processes (<;650°C) and salicide stabilization achievements. This integration scheme enables fine grain partitioning and thus a gain in performance versus cost ratio linked to separation of heterogeneous technologies on distinct levels. In this work, we will detail examples taking advantage of the unique 3-D contact pitch achieved with sequential 3-D.
Keywords :
CMOS integrated circuits; field effect transistors; three-dimensional integrated circuits; 3D contact density; 3D contact pitch; 3D schemes; 3D sequential integration; CMOS-FET; fine grain partitioning; low temperature processes; salicide stabilization; transistor scale; wafer bonding; Nanoelectronics; Sequential analysis; Temperature measurement; Three dimensional displays; 3-D monolithic integration; 3-D sequential integration; Low temperature process; molecular bonding; solid phase epitaxy; three-dimensional (3-D) integration;
fLanguage :
English
Journal_Title :
Emerging and Selected Topics in Circuits and Systems, IEEE Journal on
Publisher :
ieee
ISSN :
2156-3357
Type :
jour
DOI :
10.1109/JETCAS.2012.2223593
Filename :
6374247
Link To Document :
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