Title :
Tolerating multiple faults in multistage interconnection networks with minimal extra stages
Author :
Fan, Chenggong Charles ; Bruck, Jehoshua
Author_Institution :
Dept. of Electr. Eng., California Inst. of Technol., Pasadena, CA, USA
fDate :
9/1/2000 12:00:00 AM
Abstract :
Adams and Siegel (1982) proposed an extra stage cube interconnection network that tolerates one switch failure with one extra stage. We extend their results and discover a class of extra stage interconnection networks that tolerate multiple switch failures with a minimal number of extra stages. Adopting the same fault model as Adams and Siegel, the faulty switches can be bypassed by a pair of demultiplexer/multiplexer combinations. It is easy to show that, to maintain point to point and broadcast connectivities, there must be at least S extra stages to tolerate I switch failures. We present the first known construction of an extra stage interconnection network that meets this lower-bound. This 12-dimensional multistage interconnection network has n+f stages and tolerates I switch failures. An n-bit label called mask is used for each stage that indicates the bit differences between the two inputs coming into a common switch. We designed the fault-tolerant construction such that it repeatedly uses the singleton basis of the n-dimensional vector space as the stage mask vectors. This construction is further generalized and we prove that an n-dimensional multistage interconnection network is optimally fault-tolerant if and only if the mask vectors of every n consecutive stages span the n-dimensional vector space
Keywords :
demultiplexing; fault tolerant computing; multiplexing; multistage interconnection networks; demultiplexer; fault-tolerant construction; mask; minimal extra stages; multiple faults toleration; multiple switch failures; multiplexer; multistage interconnection networks; n-bit label; n-dimensional vector space; Broadcasting; Communication switching; Fault tolerance; Intelligent networks; Multiplexing; Multiprocessor interconnection networks; Parallel processing; Switches; Telecommunication switching;
Journal_Title :
Computers, IEEE Transactions on