Characterization and Design of Through-Silicon Via Arrays in Three-Dimensional ICs Based on Thermomechanical Modeling

Author

Zhang, Chunbo ; Li, Leijun

Author_Institution

Dept. of Mech. & Aerosp. Eng., Utah State Univ., Logan, UT, USA

Volume

58

Issue

2

fYear

2011

Firstpage

279

Lastpage

287

Abstract

A general approach has been proposed for predicting the temperature and thermal stress fields of through-silicon-via (TSV) arrays in 3-D integrated circuits (ICs) based on a coupled-field finite-element (FE) method. The heat source under consideration is the active device layers of the ICs that are operating under load. Individual and combined effects of TSV array parameters, including TSV height, diameter, spacing, and array size, on die temperature and thermal stress are predicted. Good linear relationships are identified between the proposed TSV array parameters and predicted temperature and thermal stress fields of the ICs. A 3-D FE model of two-stack field-programmable gate arrays with an embedded TSV array has been built and validated with an analytical model and verified by experimental measurements.

Keywords

field programmable gate arrays; finite element analysis; integrated circuit design; integrated circuit modelling; three-dimensional integrated circuits; coupled field finite element method; die temperature; field programmable gate arrays; thermal stress field; thermomechanical modeling; three dimensional integrated circuits; through silicon via arrays; Heating; Silicon; Stress; Temperature measurement; Thermal stresses; Thermomechanical processes; Through-silicon vias; Array; finite element (FE); integrated circuits (ICs); modeling; temperature; thermal stresses; through-silicon via (TSV);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2010.2089987

Filename

5640664