DocumentCode
1384179
Title
Zero-aliasing space compaction of test responses using multiple parity signatures
Author
Chakrabarty, Krishnendu ; Hayes, John P.
Author_Institution
Dept. of Electr. & Comput. Eng., Boston Univ., MA, USA
Volume
6
Issue
2
fYear
1998
fDate
6/1/1998 12:00:00 AM
Firstpage
309
Lastpage
313
Abstract
We present a parity-based space compaction technique that eliminates aliasing for any given fault model. The test responses from a circuit under test with a large number of primary outputs are merged into a narrow signature stream using a multiple-output parity tree. The functions realized by the different outputs of the compactor are determined by a procedure that targets the desired fault model. Experimental results for the ISCAS-85 benchmarks show that zero aliasing of single stuck-line faults can be achieved with a two output parity tree compactor. Our findings corroborate recent results on the fundamental limits of space compaction.
Keywords
built-in self test; integrated circuit testing; logic testing; BIST; ISCAS-85 benchmarks; fault model; multiple parity signatures; multiple-output parity tree; single stuck-line fault; test responses; two output parity tree compactor; zero-aliasing space compaction; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Fault detection; Hardware; Logic circuits;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.678893
Filename
678893
Link To Document