New Josephson-CMOS Interface Amplifier

Author

Wei, Daniel ; Whiteley, Stephen R. ; Zheng, Lizhen ; Park, Heejoung ; Kim, Hoki ; Van Duzer, Theodore

Author_Institution

Dept. of Electr. Eng. Comput. Sci., Univ. of Cal ifornia, Berkeley, CA, USA

Volume

21

Issue

3

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

805

Lastpage

808

Abstract

High-speed amplification from Josephson-level digital signals of a few millivolts to the volt levels employed in CMOS devices is optimally done in two stages. For the first stage we use a Josephson circuit which amplifies a few-millivolt input to several tens of millivolts. This drives a CMOS digital amplifier. The CMOS amplifier must be calibrated to compensate for random threshold voltage variations in the fabrication process; the design of a digital calibration circuit is included. Simulations of the calibrated amplifier at 300 K show a digital output of 1.8 V with a delay of 70-90 ps when fabricated in a 65 nm CMOS process. Simulations for 4 K will yield better results and are in progress.

Keywords

CMOS integrated circuits; Josephson effect; amplifiers; CMOS amplifier; CMOS devices; CMOS digital amplifier; Josephson circuit; Josephson-CMOS interface amplifier; Josephson-level digital signals; digital calibration circuit; fabrication process; high-speed amplification; random threshold voltage variations; CMOS integrated circuits; Calibration; Delay; Driver circuits; Integrated circuit modeling; Latches; Semiconductor device modeling; CMOS memory integrated circuits; Josephson amplifiers; Josephson junctions; hybrid integrated circuits; random access memories;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/TASC.2010.2088358

Filename

5640693