Title :
DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function
Author :
Lakshminarayana, Nagesh B. ; Lee, Jaekyu ; Kim, Hyesoon ; Shin, Jinwoo
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
GPGPU architectures (applications) have several different characteristics compared to traditional CPU architectures (applications): highly multithreaded architectures and SIMD-execution behavior are the two important characteristics of GPGPU computing. In this paper, we propose a potential function that models the DRAM behavior in GPGPU architectures and a DRAM scheduling policy α-SJF policy to minimize the potential function. The scheduling policy essentially chooses between SJF and FR-FCFS at run-time based on the number of requests from each thread and whether the thread has a row buffer hit.
Keywords :
DRAM chips; graphics processing units; multi-threading; scheduling; DRAM scheduling policy; GPGPU architecture; SIMD-execution behavior; dynamic random access memory; general-purpose graphics processing unit; multithreaded architecture; potential function; row buffer hit; Benchmark testing; Computer architecture; Equations; Instruction sets; Mathematical model; Processor scheduling; Random access memory; Benchmark testing; Computer architecture; DRAM scheduling; Equations; GPGPU; Instruction sets; Mathematical model; Potential function; Processor scheduling; Random access memory;
Journal_Title :
Computer Architecture Letters
DOI :
10.1109/L-CA.2011.32