• DocumentCode
    1384908
  • Title

    Integrating HDL synthesis and partitioning for multi-FPGA designs

  • Author

    Fang, Wen-Jong ; Wu, Allen C H

  • Author_Institution
    Tsinghua Univ., Beijing, China
  • Volume
    15
  • Issue
    2
  • fYear
    1998
  • Firstpage
    65
  • Lastpage
    72
  • Abstract
    The authors examine the interaction of HDL synthesis and multi-FPGA partitioning on designs with varying structural characteristics and HDL coding styles. They demonstrate that an integrated synthesis and partitioning methodology is crucial to achieving high-density designs
  • Keywords
    field programmable gate arrays; hardware description languages; high level synthesis; HDL coding styles; hardware description language synthesis; high-density designs; integrated synthesis; multi-FPGA designs; partitioning; partitioning methodology; structural characteristics; Application specific integrated circuits; Field programmable gate arrays; Hardware design languages; Integrated circuit interconnections; Integrated circuit synthesis; Logic circuits; Logic design; Process design; Routing; Testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.679209
  • Filename
    679209
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1384908