Title :
Integrating HDL synthesis and partitioning for multi-FPGA designs
Author :
Fang, Wen-Jong ; Wu, Allen C H
Author_Institution :
Tsinghua Univ., Beijing, China
Abstract :
The authors examine the interaction of HDL synthesis and multi-FPGA partitioning on designs with varying structural characteristics and HDL coding styles. They demonstrate that an integrated synthesis and partitioning methodology is crucial to achieving high-density designs
Keywords :
field programmable gate arrays; hardware description languages; high level synthesis; HDL coding styles; hardware description language synthesis; high-density designs; integrated synthesis; multi-FPGA designs; partitioning; partitioning methodology; structural characteristics; Application specific integrated circuits; Field programmable gate arrays; Hardware design languages; Integrated circuit interconnections; Integrated circuit synthesis; Logic circuits; Logic design; Process design; Routing; Testing;
Journal_Title :
Design & Test of Computers, IEEE
